Flip chip mounting is a mounting method in which a conductive bump is provided on each electrode pad portion of a semiconductor chip. These conductive bumps are electrically connected to circuit patterns on the surface of a printed circuit board to form a flip chip electronic package.
These conductive bump and circuit patterns can be connected by means of a conductive paste-like adhesive containing fine silver particles. A conductive film interposer can be positioned between the conductive bumps and the circuit patterns. Heat and pressure can then be applied to the conductive film. Alternatively, a solder bump material placed between the conductive bumps and the circuit patterns can be reflowed to electrically connect the conductive bumps to the circuit patterns.
In the above-described flip chip package, the conductive bumps of the semiconductor chip and the circuit patterns on the printed circuit board are bonded together and electrically connected as a unit. Accordingly, when the printed circuit board having the semiconductor chip mounted thereon, is subjected to repeated temperature cycling (temperature rise and fall), a difference in a coefficient of thermal expansion (CTE) between the semiconductor chip and the printed circuit board can cause a stress, which concentrates on the electrical connections between the conductive bumps of the semiconductor chip and the circuit patterns. Repeated temperature cycling can cause an open circuit or a near open circuit and the electrical connection to fail, thus lowering the reliability of the flip chip package.
The above-described stress is concentrated particularly at a corner portion of the semiconductor chip. Moreover, in a built-up multi-layered printed circuit board in which the circuit patterns are constituted in a number of layers, the stress concentration can lead to damage, not only in the electrical connection between the conductive bump and the circuit pattern on the surface of the built-up multi-layered printed circuit board, but also to cracking and an exfoliation of an insulating layer within the built-up multi-layered printed circuit board. It is desirable to have an electronic package that significantly reduces the stresses concentrated at corner portions of the semiconductor chip in the package. The packages will have increased operational field life. The present invention is directed at overcoming the problems set forth above.